Diary/2013-12-16

VHDLのinteger...

32bit以上は，ばっさり落とすのね．まあ，そうだよね，と．
つまり，

library IEEE;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

entity hoge is
end hoge;

architecture RTL of hoge is

  signal q, r : std_logic;
  signal a : std_logic_vector(63 downto 0) := X"0000000000000001";
  signal b : std_logic_vector(63 downto 0) := X"0000000100000000";

begin  -- RTL

  q <= '0' when to_integer(unsigned(a)) = 0 else '1';
  r <= '0' when to_integer(unsigned(b)) = 0 else '1';

end RTL;

ここで，qは'1'にrは'0'になる．