Takefumi MIYOSHI

Interested Fields

Quantum Computer, High-level Synthesis, Optimizing Compiler, Multi-processr, Automatic Parallelization, Reconfigurable Processor, HW/SW co-designing

biography

2021- Chief Technology Officer/Founder, QuEL, Inc.

2021- Adjunct Associate Professor, Center for Quantum Information and Quantum Biology, Osaka University

2014- Chief Executive Officer/Founder, WasaLabo, LLC.

2012- e-trees.Japan, Inc.

2017-2019 Senior Researcher, Toyota Infotechnology Center, Co, Ltd.

2010-2012 Assistant Professor, Graduate School of Information Systems, The University of Electro-Communications

2009-2010 Ph.D Resercher, Graduate School of Information Science and Engineering, Tokyo Institute of Technology

2007-2009 Assistant Professor, Graduate School of Inforamtion Science and Technology, The University of Tokyo

2007 Ph.D of Engineering, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institue of Technology

2005 Master of Engineering, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institue of Technology

Papers

Takefumi Miyoshi, "Keynote II: A Challenge of Scalable Quantum Computing Control Systems," 2023 IEEE 53rd International Symposium on Multiple-Valued Logic (ISMVL), Matsue, Japan, 2023, pp. 16-16, doi: 10.1109/ISMVL57333.2023.00010.

Takefumi Miyoshi, Keisuke Koike, Shinich Morisaka, Hidehisa Shiomi, Kazuhisa Ogawa, Yutaka Tabuchi, Makoto Negoro: "FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs," 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Belfast, United Kingdom, 2022, pp. 473-473, doi: 10.1109/FPL57034.2022.00089.

Tomoaki Tanaka, Ryosuke Higashi, Hidetaro Tanaka, Takefumi Miyoshi, Yasunori Osana, Jubee Tada, Kiyofumi Tanaka, Hironori Nakajo: "Shared Vector Register of RISC-V for the Future Hardware Acceleration", Sixth Workshop on Computer Architecture Research with RISC-V (CARRV 2022), June 18, 2022, USA

Makoto Negoro, Kazuhisa Ogawa, Takefumi MIYOSHI, Hidehisa Shiomi, Shinichi Morisaka, Mitsuki Kobachi, Kazuma Moriuchi, Ryohei Niwase, Yuta Kawai, Keisuke Koike, Satoshi Funada, Shuhei Tamate, Yutaka Tabuchi, Yasunobu Nakamura: "Superconducting qubit control with a system of an integrated microwave board and FPGA", APS March Meeting 2022, Volume 67, Number 3, March 14–18, 2022, Chicago

Y. Ishikawa, K. Yanai, K. Koike, T. Miyoshi and H. Nakajo: "Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool", ACM Proceedings of the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2017) ACM Digital Library．

Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga, "An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA", 1st International Symposium on Computing and Networking (CANDAR'13), pp. 112-121, 2013.

Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga, "Wire-Speed Implementation of Sliding-Window Aggregate Operator over Out-of-Order Data Streams", IEEE 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13), pp. 55-60, 2013.

Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, and Tsutomu Yoshinaga, "FPGA-based Implementation of Sliding-Window Aggregates over Disordered Data Streams", vol. IEICE-112, no. IEICE-CPSY2012-74, pp.105-110, 2013/01/17, Yokohama.

Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga : A Fast Handshake Join Implementation on FPGA with Adaptive Merging Network, the 25th International Conference on Scientific and Statistical Database Management (SSDBM), No. 44 pp. 1-4, 2013

Yasin OGE, Takefumi MIYOSHI, Hideyuki KAWASHIMA, Tsutomu YOSHINAGA: "Design and Implementation of a Handshake Join Architecture on FPGA", IEICE TRANSACTIONS on Information and Systems Vol.E95-D No.12 pp.2919-2927, Dec. 2012.

Hidetsugu IRIE, Takefumi MIYOSHI, Goki HONJO, Kei HIRAKI Tsugomu YOSHINAGA: "Using Cacheline Reuse Characteristics for Prefetcher Throttling", IEICE Trans. on Information and Systems, Vol.E95-D, No. 12, pp.2928-2938, Dec. 2012.

Yasin Oge, Takefumi MIYOSHI, Hideyuki Kawashima, Tsutomu Yoshinaga, "Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA", IEEE CS Proc. of 6th IEEE Int. Sympo. on Embedded Multicore SoCs (MCSoC-12), pp.84-91, Sep. 2012.

Yicheng Guan, CISSE AHMADOU DIT ADI, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie and Tsutomu Yoshinaga, "Throttling Control for Bufferless Routing in On-Chip Networks", IEEE CS Proc. of 6th IEEE Int. Sympo. on Embedded Multicore SoCs (MCSoC-12), pp.37-44, Sep. 2012.

Takefumi Miyoshi, Keigo Shima, Masaaki Kondo, Hidetsugu Irie, Hiroki Honda, and Tsutomu Yoshinaga. "FLAT: a GPU programming framework to provide embedded MPI", In Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units (GPGPU-5), pp. 20-29, Mar. 2012, London England

Junichi OHMURA, Takefumi MIYOSHI, Hidetsugu IRIE, Tsutomu YOSHINAGA, "Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster", IEICE TRANSACTIONS on Information and Systems Vol.E94-D No.12 pp.2319-2327, Dec. 2011.

Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, and Tsutomu Yoshinaga, "Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation", the 3rd Workshop on Ultra Performance and Dependable Acceleration Systems held in conjunction with ICNC'11, pp.228-234, Dec. 2011.

Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, and Tsutomu Yoshinaga, "An Implementation of Handshake Join on FPGA", International Conference on Networking and Computing (ICNC'11), pp.95-104, Dec. 2011.

Hidetsugu IRIE, Takefumi MIYOSHI, Goki HONJO, Kei HIRAKI, Tsutomu YOSHINAGA, "CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection", International Conference on Networking and Computing (ICNC'11), pp.127-133, Dec. 2011.

Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada and Tsutomu Yoshinaga, “A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine”, 21st International Conference on Field Programmable Logic and Applications, Chania, Crete, GREECE, Sep. 5-7, 2011

Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, and Tsutomu Yoshinaga, "An Efficient Path Setup for a Hybrid Photonic Network-on-Chip". International Journal of Networking and Computing, North America, 1, Jul. 2011.

Takefum Miyoshi, Kenji Kise, Hidetsugu Irie, and Tsutomu Yoshinaga "CODIE: Continuation-based Overlapping Data-transfers with Instruction Execution", International Conference on Networking and Computing (ICNC'10), pp.71-77, Nov. 2010.

Cisse Ahmadou Dit ADI,Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi and Tsutomu Yoshinaga, "An Efficient Path Setup for a Hybrid Photonic Network-on-Chip" Proc. of the 2nd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS'10), pp.156-161, Nov 2010.

Qin Wang, Junichi Ohmura, Shan Axida, Takefumi Miyoshi, Hidetsugu Irie, and Tsutomu Yoshinaga, "Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster", Proc. of the 2nd International Workshop on Parallel and Distributed Algorithms and Applications (PDAA'10), pp.243-248, Nov 2010.

Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise: Pattern-based Systematic Task Mapping for Many-core Processors, Workshop on Ultra Performance and Dependable Acceleration Systems held in conjunction with ICNC'10, pp.173-178 (November 2010).

Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise: SmartCore System for Dependable Many-core Processor with Multifunction Routers, International Conference on Networking and Computing (ICNC'10), pp.133-139 (November 2010).

Hironori Nakajo, Ryuichi Sakamoto, Takefumi Miyoshi, Satoshi Funada, and Tsutomu Yoshinaga，"OCTAVE: Scalable FPGA System for Large-Scaled Hardware Acceleration"，International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies 2010，1st June 2010, Tsukuba

Naoki Fujieda, Takefumi Miyoshi, and Kenji Kise， "SimMips: A MIPS System Simulator"， Workshop on Computer Architecture Education(WCAE) held in conjunction with MICRO-42， pp. 32-39 (December 2009).

Koh Uehara, Shimpei Sato, Takefumi Miyoshi, and Kenji Kise， "A Study of an Infrastructure for Research and Development of Many-Core Processors", Workshop on Ultra Performance and Dependable Acceleration Systems held in conjunction with PDCAT'09, pp. 414-419 (December 2009).

Kenichi Koizumi, Mary Inaba, Kei Hiraki, Yasuo Ishii, Takefumi Miyoshi and Kazuki Yoshizoe, "Triple Line‐based Playout for Go ‐‐‐ An Accelerator of Monte Carlo Go. ", 2009 International Conference on Reconfigurable Computing and FPGAs, ReConFig09, Dec. 2009, Cancun, Mexico

Shinya Takamaeda, Shimpei Watanabe, Takefumi Miyoshi, and Kenji Kise, "ScalableCore:The Concept of Practical and Low-Cost Prototyping System for Many-Core Processor Research and Education", The 4th Workshop on Architectural Research Prototyping (WARP 2009) held in conjunction with the ISCA-2009, Austin, USA (2009-06-20 Presentation) (June 2009).

Takefumi MIYOSHI and Nobuhiko SUGINO, "Cycle Based Architecture Simulation Environment Framework (MICS) and its Optimization"， IEEE TENCON, University of Hyderabad, Hyderabad, India, November 2008

Takefumi MIYOSHI and Nobuhiko SUGINO, "MICS: Cycle Based Architecture Simulation Environment for System Design"，
IPSJ Journal，Vol.49，No.10，pp.3482-3492，Oct. 2008 (in Japanese)

Takefumi MIYOSHI and Nobuhiko SUGINO, "Fine-Grain Parallelizing Compiler for SIMD Processor with Consideration of Register Slot Allocation"， IPSJ Transactions on Advanced Computing Systems, Vol.1 No.2 pp.240-249, Aug. 2008 (in Japanese)

Takefumi MIYOSHI and Nobuhiko SUGINO, "Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation", IEICE Transactions on Information and Systems, Dec. 2007, Vol. 90-D(12), pp.1967-1976

Takefumi MIYOSHI and Nobuhiko SUGINO, "Fine-grain Compensation Method with Consideration of Trade-offs between Computation and Data Transfer for Power Consumption", International Workshop on Advanced Low Power Systems, Seattle, Jun. 2007

Takefumi MIYOSHI and Nobuhiko SUGINO, "Unified Phase Compiler by Use of 3-D Representation Space", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E88-A, pages 838-845, April 2005

Takefumi MIYOSHI and Nobuhiko SUGINO， "An Approach to Unified Phase Compiler by Use of 3-D Representation Space"， IEEE TENCON, Chiang Mai, Thailand, November 2004

Takefumi MIYOSHI and Nobuhiko SUGINO， "A Tool and Technique to Analyze DSP Program with Dynamic Element Using 3D Representation Space"，ITC-CSCC, Korea, July 2003

Social Activities

The 2018 International Conference on Field-Programmable Technology, Supporter chair, 2018

The 2013 International Conference on Field-Programmable Technology, Demo Session Chairs, 2013

3rd Workshop on Ultra Performance and Dependable Acceleration Systems, Program Vice Chair, 2011

2nd Workshop on Ultra Performance and Dependable Acceleration Systems, Program Vice Chair, 2010

Workshop on Ultra Performance and Dependable Acceleration Systems, Publication Chair, 2009

Talk

"[Invited] Overview about A.I or Deep-learning", Artificial Intelligence Seminar, 30th Jan. 2018, Philippines Cebu

"FPGA Development", SIST Open Lecture, 9th May 2015, Hanoi University of Science and Technology, Vietnum Hanoi

Misc

Synthesijer - http://synthesijer.github.io/web/

A compiler from Java to VHDL and Verilog HDL

JavaRock - http://javarock.sourceforge.net/

JavaRock is a compiler of Java into VHDL

MICS - http://mics.sourceforge.jp/

MICS is Cycle-based Simulator based on abstracted hardware definition

Private Web Page(in Japanese) - http://www.wasamon.net/miyo/

hobby, diary, etc.